The present disclosure relates generally to the field of integrated circuit fabrication and methods of forming polysilicon layers employed therein.
The demand for storage devices that have a small package size and a high storage density have increased due to the creation of many new applications that require high density storage devices. Accordingly, semiconductor device geometries continue to dramatically decrease in size, to the extent that existing devices routinely have feature geometries smaller than 65 nm.
However, the manufacture of memory devices and other storage devices are plagued by a myriad of problems, often attributable to topographic differences between memory devices and supporting microelectronic devices. Such problems may be associated with over-etching, over-planarizing, and/or otherwise damaging some features, while other features go undamaged.
Accordingly, what is needed in the art is an integrated circuit device and method of manufacture thereof that addresses the above discussed issues.